The Inter-Integrated Circuit (I2C) specification defines transactions between masters and slaves over an I2C bus that uses only two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock Line (SCL), pulled up with resistors. FIG. 1 is a timing diagram illustrating a protocol for data communications between a master and a slave over the SDA and SCL lines. The data transfer is initiated with a start bit S when SDA is pulled low while SCL stays high. Then, seven address bits are transferred followed by a read/write bit R/W/indicating whether the data bytes in the transaction are being read or written. Acknowledgement bits ACK are transferred to acknowledge receipt of preceding information. When the data transfer is complete, a stop bit P is sent by releasing the SDA line to allow it to be pulled up while SCL is maintained high.
FIG. 2 illustrates a simplified format of a serial data transaction between a master and a slave. The serial data transaction is initiated by the start bit S transferred from the master. The start bit field S is followed by the 7-bit slave address field identifying the slave addressed by the master. The read/write bit field R/W/ indicates whether the master writes or reads the DATA bytes. The “0” bit indicates that the master writes the data to the slave. The slave responds with the acknowledgement bit A. By pulling the SDA low, the slave acknowledges receipt of the information from the slave. When the SDA is high, the receipt is not acknowledged. The data transfer ends with the stop bit P transferred from the master to the slave.
The I2C specification allocates a 7-bit word to the address field of a standard I2C transaction allowing up to 128 slave devices on a single I2C bus. However, most slave devices can be configured to only a limited number of different addresses, for example, to one of eight different I2C addresses. This restricts the number of identical slave devices on an I2C bus. For example, if each slave device can be configured to one of eight different I2C addresses, only eight slave devices of the same type could appear on one I2C bus.
Another difficulty commonly faced by system designers is that identical add-in cards may connect to a shared backplane. It would be desirable to use a single I2C bus to communicate with all of the add-in cards, but this is not possible because the cards respond to identical I2C addresses.
In these situations, the system designer usually splits one I2C bus into multiple buses using an I2C multiplexer. This requires additional I2C transactions with the multiplexer connecting the appropriate bus when communicating with a specific slave or add-in card. This consumes valuable bandwidth and adds complexity to the firmware implementation.
Therefore, there is a need in an address translation device that would translate a slave address indicated by a master to other addresses selected so as to allow up to 128 slave devices to connect to a single bus even when the slaves are configured to respond to only a limited number of addresses.